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? idt and the idt logo are regi stered trademarks of integrated device technology, inc. ? 2013 integrated device technology, inc 1 of 35 december 17, 2013 device overview the 89HPES32NT8BG2 is a member of the idt family of pci express? switching solutions. t he pes32nt8bg2 is a 32-lane, 8-port system interconnect switch optimiz ed for pci express gen2 packet switching in high-performance applicat ions, supporting multiple simulta- neous peer-to-peer traffic flows. tar get applications include multi-host or intelligent i/o based systems w here inter-domain communication is required, such as servers, storage, communications, and embedded systems. features ? high performance non-blo cking switch architecture ? 32-lane, 8-port pcie switch with flexible port configuration ? integrated serdes supports 5.0 gt/s gen2 and 2.5 gt/s gen1 operation ? delivers up to 32 gbps (256 gbps) of switching capacity ? supports 128 bytes to 2 kb maximum payload size ? low latency cut-through architecture ? supports one virtual channel and eight traffic classes ? port configurability ? eight x4 switch ports ? adjacent x4 ports can be merged to achieve x8 port widths ? automatic per port link width negotiation (x8 --> x4 --> x2 --> x1) ? crosslink support ? automatic lane reversal ? per lane serdes configuration ? de-emphasis ? receive equalization ? drive strength ? innovative switch pa rtitioning feature ? supports up to 8 fully independent switch partitions ? logically independent switches in the same device ? configurable downstream port device numbering ? supports dynamic reconfigur ation of switch partitions ? dynamic port reconfigurat ion ? downstream, upstream, non-transparent bridge ? dynamic migration of ports between partitions ? movable upstream port within and between switch partitions ? non-transparent brid ging (ntb) support ? supports up to 8 nt endpoints per switch, each endpoint can communicate with other switch partitions or external pcie domains or cpus ? 6 bars per nt endpoint ? bar address translation ? all bars support 32/64-bit bas e and limit address translation ? two bars (bar2 and bar4) support look-up table based address translation ? 32 inbound and outbound doorbell registers ? 4 inbound and outbound message registers ? supports up to 64 masters ? unlimited number of outstanding transactions ? multicast ? compliant with the pci-sig multicast ? supports 64 multicast groups ? supports multicast across non-transparent port ? multicast overlay mechanism support ? ecrc regeneration support ? integrated direct memory access (dma) controllers ? supports up to 2 dma upstream ports, each with 2 dma chan- nels ? supports 32-bit and 64-bit memory-to-memory transfers ? fly-by translation provides reduced latency and increased performance over buffered approach ? supports arbitrary source a nd destination address alignment ? supports intra- as well as in ter-partition data transfers using the non-transparent endpoint ? supports dma transfers to multicast groups ? linked list descriptor-based operation ? flexible addressing modes ? linear addressing ? constant addressing ? quality of service (qos) ? port arbitration ? round robin ? request metering ? idt proprietary feature that balances bandwidth among switch ports for maximum system throughput ? high performance switch core architecture ? combined input output queued (cioq) switch architecture with large buffers ? clocking ? supports 100 mhz and 125 mhz reference clock frequencies ? flexible port clocking modes ? common clock ? non-common clock ? local port clock with ssc (spr ead spectrum setting) and port reference clock input 89HPES32NT8BG2 datasheet 32-lane 8-port pcie? gen2 system interconnect switch
idt 89HPES32NT8BG2 datasheet 2 of 35 december 17, 2013 ? hot-plug and hot swap ? hot-plug controller on all ports ? hot-plug supported on all downstream switch ports ? all ports support hot-plug us ing low-cost external i 2 c i/o expanders ? configurable presence-detect supports card and cable appli- cations ? gpe output pin for hot-plug event notification ? enables sci/smi generation for legacy operating system support ? hot-swap capable i/o ? power management ? supports d0, d3hot and d3 power management states ? active state power management (aspm) ? supports l0, l0s, l1, l2/l3 ready, and l3 link states ? configurable l0s and l1 entry timers allow performance/ power-savings tuning ? serdes power savings ? supports low swing / half-swing serdes operation ? serdes associated with unused ports are turned off ? serdes associated with unused lanes are placed in a low power state ? reliability, availability, and serviceability (ras) ? ecrc support ? aer on all ports ? secded ecc protection on all internal rams ? end-to-end data path parity protection ? checksum serial eeprom content protected ? ability to generate an interrupt (intx or msi) on link up/down transitions ? initialization / configuration ? supports root (bios, os, or driver), serial eeprom, or smbus switch initialization ? common switch configurations are supported with pin strap- ping (no external components) ? supports in-system serial eep rom initialization/program- ming ? on-die temperature sensor ? range of 0 to 127.5 degrees celsius ? three programmable temperature thresholds with over and under temperature threshold alarms ? automatic recording of maximum high or minimum low temperature ? 9 general purpose i/o ? test and debug ? ability to inject aer errors simplifies in system error handling software validation ? on-chip link activity and status outputs available for several ports ? per port link activity and status outputs available using external i 2 c i/o expander for all remaining ports ? supports ieee 1149.6 ac jtag and ieee 1149.1 jtag ? standards and compatibility ? pci express base specification 2.1 compliant ? implements the following optional pci express features ? advanced error reporting (aer) on all ports ? end-to-end crc (ecrc) ? access control services (acs) ? device serial number enhanced capability ? sub-system id and sub-system vendor id capability ? internal error reporting ? multicast ? vga and isa enable ? l0s and l1 aspm ? ari ? power supplies ? requires three power supply voltages (1.0v, 2.5v, and 3.3v) ? packaged in a 23mm x 23mm 484- ball flip chip bga with 1mm ball spacing product description with non-transparent bridging f unctionality and innovative switch partitioning feature, the pes32nt8bg 2 allows true multi-host or multi- processor communications in a single device. integrated dma control- lers enable high-performance system design by off-loading data transfer operations across memories from t he processors. each lane is capable of 5 gt/s link speed in both directi ons and is fully compliant with pci express base specification 2.1. a non-transparent bridge (ntb) is required when two pci express domains need to communicate to each other. the main function of the ntb block is to initialize and translate addresses and device ids to allow data exchange across pci express domains. the major function- alities of the ntb block are summarized in table 1.
idt 89HPES32NT8BG2 datasheet 3 of 35 december 17, 2013 block diagram figure 1 pes32nt8bg2 block diagram smbus interface the pes32nt8bg2 contains two smbus interfaces . the slave interface provides full access to the configuration registers in the p es32nt8bg2, allowing every configuration regi ster in the device to be read or written by an external agent. the master interface allows the default configuration register values of the pes32nt8bg2 to be overridden following a reset with values pr ogrammed in an external serial eeprom. the master interface is also used by an external hot-plug i/o expander. function number description ntb ports up to 8 each device can be configured to have up to 8 ntb functions and can support up to 8 cpus/roots. mapping table entries up to 64 for entire device each device can have up to 64 masters id for address and id translations. mapping windows six 32-bits or three 64-bits each nt port has six bars, where each bar opening an nt window to another domain. address translation direct-address and lookup table trans- lations lookup-table translation divides the bar aperture into up to 24 segments, where each segment has independent translation programming and is associated with an entry in a look-up table. doorbell registers 32 bits doorbell register is used for event signaling between domains, where an outbound doorbell bit sets a corresponding bit at the inbound doorbell in the other domain. message registers 4 inbound and out- bound registers of 32-bits message registers allow mailbox message passing between domains -- message placed in the inbound register will be seen at the outbound register at the other domain. table 1 non-transparent bridge function summary 8-port switch core / 32 gen2 pci express lanes frame buffer route table port arbitration scheduler serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer (port 0) (port 2) (port 20) (ports 4, 6, 8, 12, 16)
idt 89HPES32NT8BG2 datasheet 4 of 35 december 17, 2013 each of the two smbus interfaces contai n an smbus clock pin and an smbus data pin. in addition, the slave smbus has the ssmbadd r2 pin. as shown in figure 2 , the master and slave smbuses may only be used in a split configur ation. in the split configuration, the master and slave smbu ses operate as two independent buses; thus, multi-ma ster arbitration is not required. the smbus master interface does not support s mbus arbitration. as a result, the switch?s smbus master must be the only master in the smbus lines that connect to the serial eeprom and i/o expand er slaves. figure 2 split smbus interface configuration hot-plug interface the pes32nt8bg2 supports pci express hot- plug on each downstream port. to reduce the num ber of pins required on the device, the pes32nt8bg2 utilizes an external i/o expander, such as that used on pc motherboards, connected to the smbus master interface. f ollowing reset and configuration, whenever the state of a hot-plug output needs to be modified, the pes32nt8bg2 generates an smbus transaction to the i/o expander with the new value of all of the outputs. whenever a hot-plug input changes, the i/o expander generates an interrupt w hich is received on the ioexpintn input pin (alternate functi on of gpio) of the pes32nt8bg2. in response to an i/o expander interrupt, the pes32nt8 bg2 generates an smbus transaction to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes32nt8bg2 provides 9 general purpos e i/o (gpio) pins that may be individua lly configured as general purpose inputs, gener al purpose outputs, or alternate functions. all gpio pins are shared with other on-chip function s. these alternate functions may be enable d via software, smbus slave interface, or serial configuration eeprom. processor switch ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... hot-plug i/o expander
idt 89HPES32NT8BG2 datasheet 5 of 35 december 17, 2013 pin description the following tables list the functions of the pins provided on the pes32nt8bg2. some of the functions listed may be multiplexe d onto the same pin. the active polarity of a signal is defined using a suff ix. signals ending with an ?n? are defined as being active, or asse rted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines ) will be interpreted as bei ng active, or asserted, wh en at a logic one (high) level. differential signals end with a suffix ?n? or ?p.? the different ial signal ending in ?p? is the positive portion of the differe ntial pair and the differential signal ending in ?n? is the negative portion of the differential pair. note: pin [x] of a port refers to a lane. for port 0, pe00rn[0] refers to lane 0, pe00rn[1] refers to lane 1, etc. signal type name/description pe00rn[3:0] pe00rp[3:0] i pci express port 0 serial data receive. differential pci express receive pairs for port 0. pe00tn[3:0] pe00tp[3:0] o pci express port 0 serial data transmit. differential pci express transmit pairs for port 0. pe02rn[3:0] pe02rp[3:0] i pci express port 2 serial data receive. differential pci express receive pairs for port 2. pe02tn[3:0] pe02tp[3:0] o pci express port 2 serial data transmit. differential pci express transmit pairs for port 2. pe04rn[3:0] pe04rp[3:0] i pci express port 4 serial data receive. differential pci express receive pairs for port 4. pe04tn[3:0] pe04tp[3:0] o pci express port 4 serial data transmit. differential pci express transmit pairs for port 4. pe06rn[3:0] pe06rp[3:0] i pci express port 6 serial data receive. differential pci express receive pairs for port 6. pe06tn[3:0] pe06tp[3:0] o pci express port 6 serial data transmit. differential pci express transmit pairs for port 6. pe08rn[3:0] pe08rp[3:0] i pci express port 8 serial data receive. differential pci express receive pairs for port 8. pe08tn[3:0] pe08tp[3:0] o pci express port 8 serial data transmit. differential pci express transmit pairs for port 8. pe12rn[3:0] pe12rp[3:0] i pci express port 12 serial data receive. differential pci express receive pairs for port 12. pe12tn[3:0] pe12tp[3:0] o pci express port 12 serial data transmit. differential pci express transmit pairs for port 12. pe16rn[3:0] pe16rp[3:0] i pci express port 16 serial data receive. differential pci express receive pairs for port 16. pe16tn[3:0] pe16tp[3:0] o pci express port 16 serial data transmit. differential pci express transmit pairs for port 16. pe20rn[3:0] pe20rp[3:0] i pci express port 20 serial data receive. differential pci express receive pairs for port 20. pe20tn[3:0] pe20tp[3:0] o pci express port 20 serial data transmit. differential pci express transmit pairs for port 20. table 2 pci express interface pins
idt 89HPES32NT8BG2 datasheet 6 of 35 december 17, 2013 signal type name/description gclkn[1:0] gclkp[1:0] i global reference clock. differential reference clock input pairs. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic. the frequency of the differential reference clock is determined by the gclkfsel signal. note: both pairs of the global reference clocks must be connected to and derived from the same clock source. refer to the overview section of chapter 2 in the pes32nt8xg2 user manual for additional details. p00clkn p00clkp i port reference clock . differential reference clock pair associated with port 0. p02clkn p02clkp i port reference clock . differential reference clock pair associated with port 2. p04clkn p04clkp i port reference clock . differential reference clock pair associated with port 4. table 3 reference clock pins signal type name/description msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. it is active and generating the clock only when the eeprom or i/o expanders are being accessed. msmbdat i/o master smbus data. this bidirectional signal is used for data on the master smbus. ssmbaddr[2] i slave smbus address. this pin determines the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize transfers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 4 smbus interface pins
idt 89HPES32NT8BG2 datasheet 7 of 35 december 17, 2013 signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: part0perstn 1st alternate function pin type: input/output 1st alternate function: assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd alternate function pin name: p16linkupn 2nd alternate function pin type: output 2nd alternate function: port 16 link up status output. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: part1perstn 1st alternate function pin type: input/output 1st alternate function: assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd alternate function pin name: p16activen 2nd alternate function pin type: output 2nd alternate function: port 16 link active status output. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: part2perstn 1st alternate function pin type: input/output 1st alternate function: assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd alternate function pin name: p4linkupn 2nd alternate function pin type: output 2nd alternate function: port 4 link up status output. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: part3perstn 1st alternate function pin type: input/output 1st alternate function: assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd alternate function pin name: p4activen 2nd alternate function pin type: output 2nd alternate function: port 4 link active status output. gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: failover0 1st alternate function pin type: input 1st alternate function: when this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. 2nd alternate function pin name: p0linkupn 2nd alternate function pin type: output 2nd alternate function: port 0 link up status output. gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: gpen 1st alternate function pin type: output 1st alternate function: hot-plug general purpose even output. 2nd alternate function pin name: p0activen 2nd alternate function pin type: output 2nd alternate function: port 0 link active status output. table 5 general purpose i/o pins (part 1 of 2)
idt 89HPES32NT8BG2 datasheet 8 of 35 december 17, 2013 gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: failover1 1st alternate function pin type: input 1st alternate function: when this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. 2nd alternate function pin name: failover3 2nd alternate function pin type: input 2nd alternate function: when this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: failover2 1st alternate function pin type: input 1st alternate function: when this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. 2nd alternate function pin name: p8linkupn 2nd alternate function pin type: output 2nd alternate function: port 8 link up status output. gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: ioexpintn 1st alternate function pin type: input 1st alternate function: io expander interrupt. 2nd alternate function pin name: p8activen 2nd alternate function pin type: output 2nd alternate function: port 8 link active status output. signal type name/description stk0cfg0 i stack 0 configuration. this pin selects the configuration of stack 0. stk1cfg0 i stack 1 configuration. this pin selects the configuration of stack 1. stk2cfg0 i stack 2 configuration. this pin selects the configuration of stack 2. stk3cfg0 i stack 3 configuration. this pin selects the configuration of stack 3. table 6 stack configuration pins signal type name/description clkmode[1:0] i clock mode. these signals determine the port clocking mode used by ports of the device. gclkfsel i global clock frequency select. these signals select the frequency of the gclkp and gclkn signals. 0x0 100 mhz 0x1 125 mhz table 7 system pins (part 1 of 2) signal type name/description table 5 general purpose i/o pins (part 2 of 2)
idt 89HPES32NT8BG2 datasheet 9 of 35 december 17, 2013 perstn i fundamental reset. assertion of this signal resets all logic inside the device. rsthalt i reset halt. when this signal is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device operation begins. the device exits the quasi-reset state when the rsthalt bit is cleared in the swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pins determine the switch operating mode. these pins should be static and not change following the negation of perstn. 0x0 - single partition 0x1 - single partition with serial eeprom initialization 0x2 - single partition with seri al eeprom jump 0 initialization 0x3 - single partition with seri al eeprom jump 1 initialization 0x4 through 0x7 - reserved 0x8 - single partition with reduced latency 0x9 - single partition with serial eepr om initialization and reduced latency 0xa - multi-partition with unattached ports 0xb - multi-partition with unattached ports and i 2 c reset 0xc - multi-partition with unattached ports and serial eeprom initialization 0xd - multi-partition with unattached ports with i 2 c reset and serial eeprom initial- ization 0xe - multi-partition with disabled ports 0xf - multi-partition with disabled ports and serial eeprom initialization signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller . jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 8 test pins signal type name/description table 7 system pins (part 2 of 2)
idt 89HPES32NT8BG2 datasheet 10 of 35 december 17, 2013 signal type name/description refres[7:0] ? external reference resistor. reference for the corresponding serdes bias currents and pll calibration circuitry. a 3k ohm +/- 1% resistor should be connected from this pin to ground and isolated from any source of noise injection. each bit of this signal corresponds to a serdes quad, e.g., refres[5] is the reference resistor for serdes quad 5. refrespll ? pll external reference resistor. provides a reference for the pll bias currents and pll calibration circuitry. a 3k ohm +/- 1% resistor should be connected from this pin to ground and isolated from any source of noise injection. v dd core ? core v dd. power supply for core logic (1.0v). v dd i/o ? i/o v dd. lvttl i/o buffer power supply (3.3v). v dd pea ? pci express analog power. serdes analog power supply (1.0v). v dd peha ? pci express analog high power. serdes analog power supply (2.5v). v dd peta ? pci express transmitter analog voltage. serdes transmitter analog power supply (1.0v). v ss ? ground. table 9 power, ground, and serdes resistor pins
idt 89HPES32NT8BG2 datasheet 11 of 35 december 17, 2013 pin characteristics note: some input pads of the switch do not contain internal pull-ups or pull-downs. unused smbus and system inputs should be tied off to appropriate levels. this is especially critical for unused contro l signal inputs which, if left floating, could adversely affec t operation. also, floating pins can cause a slight increase in power consumption. unused serdes (rx and tx) pins should be left floating. finally, no conn ection pins should not be connected. function pin name type buffer i/o type internal resistor 1 notes pci express interface pe00rn[3:0] i pcie differential 2 serial link note: unused serdes pins can be left floating pe00rp[3:0] i pe00tn[3:0] o pe00tp[3:0] o pe02rn[3:0] i pe02rp[3:0] i pe02tn[3:0] o pe02tp[3:0] o pe04rn[3:0] i pe04rp[3:0] i pe04tn[3:0] o pe04tp[3:0] o pe06rn[3:0] i pe06rp[3:0] i pe06tn[3:0] o pe06tp[3:0] o pe08rn[3:0] i pe08rp[3:0] i pe08tn[3:0] o pe08tp[3:0] o pe12rn[3:0] i pe12rp[3:0] i pe12tn[3:0] o pe12tp[3:0] o pe16rn[3:0] i pe16rp[3:0] i pe16tn[3:0] o pe16tp[3:0] o pci express interface (cont.) pe20rn[3:0] i pcie differential serial link pe20rp[3:0] i pe20tn[3:0] o pe20tp[3:0] o table 10 pin characteristics (part 1 of 2)
idt 89HPES32NT8BG2 datasheet 12 of 35 december 17, 2013 reference clocks gclkn[1:0] i hcsl diff. clock input refer to table 11 note: unused port clock pins should be connected to vss on the board. gclkp[1:0] i p00clkn i p00clkp i p02clkn i p02clkp i p04clkn i p04clkp i smbus msmbclk i/o lvttl sti 3 note: when unused, these signals must be pulled up on the board using an external resistor or current source in accordance with the smbus specifica- tion. msmbdat i/o sti ssmbaddr[2] i pull-up ssmbclk i/o sti note: when unused, these signals must be pulled up on the board using an external resistor or current source in accordance with the smbus specifica- tion. ssmbdat i/o sti general purpose i/o gpio[8:0] i/o lvttl sti, high drive pull-up unused pins can be left floating. stack configuration stk0cfg0 i lvttl input pull-down unused pins can be left floating. stk1cfg0 i stk2cfg0 i stk3cfg0 i system pins clkmode[1:0] i lvttl input pull-up unused pins can be left floating. gclkfsel i pull-down perstn i schmitt trigger rsthalt i pull-down unused pins can be left floating. swmode[3:0] i pull-down ejtag / jtag jtag_tck i lvttl sti pull-up unused pins can be left floating. jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up serdes reference resis- tors refres[7:0] ? analog unused pins should be connected to vss on the board. refrespll ? 1. internal resistor val ues under typical operat ing conditions are 92k ? for pull-up and 91k ?? for pull-down. 2. all receiver pins set the dc common mode voltage to gr ound. all transmitters must be ac coupled to the media. 3. schmitt trigger input (sti). function pin name type buffer i/o type internal resistor 1 notes table 10 pin characteristics (part 2 of 2)
idt 89HPES32NT8BG2 datasheet 13 of 35 december 17, 2013 logic diagram ? pes32nt8bg2 figure 3 pes32nt8bg2 logic diagram jtag_tck gpio[8:0] 9 general purpose i/o msmbclk msmbdat master smbus interface jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins p00clkn p00clkp pe00rp[3:0] pe00rn[3:0] pe00tp[3;0] pe00tn[3:0] pe02tp[3:0] pe02tn[3:0] pe06tp[3:0] pe06tn[3:0] pe20tp[3:0] pe20tn[3:0] pcie switch serdes output port 20 pes32nt8bg2 pcie switch serdes input port 0 pcie switch serdes output port 2 pcie switch serdes output port 0 pcie switch serdes output port 6 global reference clocks gclkn[1:0] gclkp[1:0] gclkfsel v dd core v dd i/o v dd pea power/ground v ss v dd peha v dd peta rsthalt system pins swmode[3:0] 4 clkmode[1:0] perstn 2 pe04tp[3:0] pe04tn[3:0] pcie switch serdes output port 4 pe08tp[3:0] pe08tn[3:0] pcie switch serdes output port 8 pe12tp[3:0] pe12tn[3:0] pcie switch serdes output port 12 pe16tp[3:0] pe16tn[3:0] pcie switch serdes output port 16 stk[3:0]cfg0 4 ssmbclk ssmbdat slave smbus interface ssmbaddr[2] p02clkn p02clkp pe02rp[3:0] pe02rn[3:0] pcie switch serdes input port 2 p04clkn p04clkp pe04rp[3:0] pe04rn[3:0] pcie switch serdes input port 4 pe06rp[3:0] pe06rn[3:0] pcie switch serdes input port 6 pe08rp[3:0] pe08rn[3:0] pcie switch serdes input port 8 pe12rp[3:0] pe12rn[3:0] pcie switch serdes input port 12 pe16rp[3:0] pe16rn[3:0] pcie switch serdes input port 16 pe20rp[3:0] pe20rn[3:0] pcie switch serdes input port 20 refres[7:0] serdes reference resistors refrespll 8
idt 89HPES32NT8BG2 datasheet 14 of 35 december 17, 2013 system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 16 and 15. note: refclk jitter compliant to pcie gen2 common clock architecture is adequate for the gclkn/p[x] and pe[x]clkn/p pins of this idt pcie switch. this same jitter specificat ion is applicable when interfacing the switch to another idt switch in a separate (non -common) clock architecture. ac timing characteristics parameter description condition min typical max unit refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be eit her 100 or 125 mhz depending on signal gclkfsel . mhz t c-rise rising edge rate differential 0.6 4 v/ns t c-fall falling edge rate differential 0.6 4 v/ns v ih differential input high voltage differential +150 mv v il differential input low voltage differential -150 mv v cross absolute single-ended crossing point voltage single-ended +250 +550 mv v cross-delta variation of v cross over all rising clock edges single-ended +140 mv v rb ring back voltage margin differential -100 +100 mv t stable time before v rb is allowed differential 500 ps t period-avg average clock period accuracy -300 2800 ppm t period-abs absolute period, including spread-spec- trum and jitter 9.847 10.203 ns t cc-jitter cycle to cycle jitter 150 ps v max absolute maximum input voltage +1.15 v v min absolute minimum input voltage -0.3 v duty cycle duty cycle 40 60 % rise/fall matching single ended rising refclk edge rate ver- sus falling refclk edge rate 20 % z c-dc clock source output dc impedance 40 60 ? table 11 input clock requirements parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 pcie transmit ui unit interval 399.88 400 400.12 199.94 200 200.06 ps t tx-eye minimum tx eye width 0.75 0.75 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maxi- mum deviation from the median 0.125 ui table 12 pcie ac timing characteristics (part 1 of 2)
idt 89HPES32NT8BG2 datasheet 15 of 35 december 17, 2013 figure 4 gpio ac timing waveform t tx-rise , t tx-fall tx rise/fall time: 20% - 80% 0.125 0.15 ui t tx- idle-min minimum time in idle 20 20 ui t tx-idle-set-to- idle maximum time to transition to a valid idle after sending an idle ordered set 88 ns t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 8 8 ns t tx-skew transmitter data skew between any 2 lanes 1.3 1.3 ns t min-pulsed minimum instantaneous lone pulse width na 0.9 ui t tx-hf-dj-dd transmitter deterministic jitter > 1.5mhz bandwidth na 0.15 ui t rf-mismatch rise/fall time differential mismatch na 0.1 ui pcie receive ui unit interval 399.88 400 400.12 199.94 200.06 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-skew lane to lane input skew 20 8 ns t rx-hf-rms 1.5 ? 100 mhz rms jitter (common clock) na 3.4 ps t rx-hf-dj-dd maximum tolerable dj by the receiver (common clock) na 88 ps t rx-lf-rms 10 khz to 1.5 mhz rms jitter (common clock) na 4.2 ps t rx-min-pulse minimum receiver instantaneous eye width na 0.6 ui 1. minimum, typical, and maximum values meet the re quirements under pci express base specification 2.1. signal symbol reference edge min max unit timing diagram reference gpio gpio[8:0] 1 1. gpio signals must meet the setup and hold times if t hey are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determ ined by calculation, not by testing. none 50 ? ns see figure 4 . table 13 gpio ac timing characteristics parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 table 12 pcie ac timing characteristics (part 2 of 2) tpw_13b extclk gpio (asynchronous input)
idt 89HPES32NT8BG2 datasheet 16 of 35 december 17, 2013 figure 5 jtag ac timing waveform signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 5 . thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_t ms should be held at 1 while t he signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_ n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to eit her the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determ ined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 14 jtag ac timing characteristics tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
idt 89HPES32NT8BG2 datasheet 17 of 35 december 17, 2013 recommended operating temperature recommended operating supply voltages ? commercial temperature recommended operating supply volt ages ? industrial temperature power-up/power-down sequence during power supply ramp-up, v dd core must remain at least 1.0v below v dd i/o at all times. there are no other power-up sequence require- ments for the various operating supply voltages. the power-down sequence can occur in any order. grade temperature commercial 0 ? c to +70 ? c ambient industrial -40 ? c to +85 ? c ambient table 15 pes32nt8bg2 operating temperatures symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes 3.125 3.3 3.465 v v dd pea 1 1. v dd pea and v dd peta should have no more than 25mv peak-peak ac power supply noise superimposed on the 1.0v nominal dc value. pci express analog power 0.95 1.0 1.1 v v dd peha 2 2. v dd peha should have no more than 50mv peak-peak ac power supply noise superimposed on the 2.5v nominal dc value. pci express analog high power 2.25 2.5 2.75 v v dd peta 1 pci express transmitter analog voltage 0.95 1.0 1.1 v v ss common ground 0 0 0 v table 16 pes32nt8bg2 operating vo ltages ? commercial temperature symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes 3.125 3.3 3.465 v v dd pea 1 1. v dd pea and v dd peta should have no more than 25mv peak-peak ac power supply noise superimposed on the 1.0v nominal dc value. pci express analog power 0.95 1.0 1.05 v v dd peha 2 2. v dd peha should have no more than 50mv peak-peak ac power supply noise superimposed on the 2.5v nominal dc value. pci express analog high power 2.25 2.5 2.75 v v dd peta 1 pci express transmitter analog voltage 0.95 1.0 1.1 v v ss common ground 0 0 0 v table 17 pes32nt8bg2 operating vo ltages ? industrial temperature
idt 89HPES32NT8BG2 datasheet 18 of 35 december 17, 2013 power consumption typical power is measured under the follow ing conditions: 25c ambient, 35% total li nk usage on all ports, typical voltages def ined in table 16 (and also listed below). maximum power is measured under the follow ing conditions: 70c ambient, 85% total link usage on all ports, maximum voltages def ined in table 16 (and also listed below). note 1 : the above power consumption assumes that all ports are func tioning at gen2 (5.0 gt/s) speeds. power consumption can be reduced by turning off unused ports through software or through boot eepr om. power savings will occur in v dd pea, v dd peha, and v dd peta. power savings can be estimated as di rectly proportional to the number of unused por ts, since the power consumption of a t urned- off port is close to zero. for example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be calculated quite simply as 3/16 multiplied by t he power consumption indicated in the above table. note 2 : using a port in gen1 mode (2.5gt/s) results in appr oximately 18% power savings for each power rail: v dd pea, v dd peha, and v dd peta. number of active lanes per port core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 2.5v max 2.75v typ 1.0v max 1.1v typ 3.3v max 3.465 typ power max power x8/x8/x8/x4/x4 (full swing) ma 2486 3400 1623 1806 230 234 679 729 3 5 watts 2.49 3.74 1.62 1.99 0.58 0.64 0.68 0.80 0.01 0.02 5.38 7.19 x8/x8/x8/x4/x4 (half swing) ma 2486 3400 1396 1553 230 234 353 379 3 5 watts 2.49 3.74 1.40 1.71 0.58 0.64 0.35 0.42 0.01 .02 4.83 6.53 table 18 pes32nt8bg 2 power consumption
idt 89HPES32NT8BG2 datasheet 19 of 35 december 17, 2013 thermal considerations this section describes thermal cons iderations for the pes32nt8bg2 (23mm 2 fcbga484 package). the data in table 19 below contains informa- tion that is relevant to the thermal performance of the pes32nt8bg2 switch. note: it is important for the reliability of this device in any user environment that the juncti on temperature not exceed the t j(max) value specified in table 19 . consequently, the effective junction to ambient thermal resistance ( ? ja ) for the worst case scenario must be maintained below the value determined by the formula: ? ja = (t j(max) - t a(max) )/p given that the values of t j(max) , t a(max) , and p are known, the value of desired ? ja becomes a known entity to the system designer. how to achieve the desired ? ja is left up to the board or system designer, but in general, it can be achieved by adding the effects of ? jc (value provided in table 19 ), thermal resistance of the chosen adhesive ( ? cs ), that of the heat sink ( ? sa ), amount of airflow, and properties of the circuit board (number of layers and size of the board). it is strongly recommended that users per form their own thermal analysi s for their own board and system design scenarios. symbol parameter value units conditions t j(max) junction temperature 125 o cmaximum t a(max) ambient temperature 70 o c maximum for commercial-rated products 85 o c maximum for industrial-rated products ? ja(effective) effective thermal resistance, junction-to-ambient 15.2 o c/w zero air flow 8.5 o c/w 1 m/s air flow 7.1 o c/w 2 m/s air flow ? jb thermal resistance, junction-to-board 3.1 o c/w ? jc thermal resistance, junction-to-case 0.15 o c/w p power dissipation of the device 7.19 watts maximum table 19 thermal specifications for pes32nt8bg2, 23x23 mm fcbga484 package
idt 89HPES32NT8BG2 datasheet 20 of 35 december 17, 2013 dc electrical characteristics values based on systems running at re commended supply voltages, as shown in table 16 . note: see table 10 , pin characteristics, for a complete i/o listing. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 800 1200 mv v tx-diffp-p-low low-drive differential peak to peak output voltage 400 1200 400 1200 mv v tx-de-ratio- 3.5db de-emphasized differential out- put voltage -3 -4 -3.0 -3.5 -4.0 db v tx-de-ratio- 6.0db de-emphasized differential out- put voltage na -5.5 -6.0 -6.5 db v tx-dc-cm dc common mode voltage 0 3.6 0 3.6 v v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 25 mv v tx-idle-diffp electrical idle diff peak output 20 20 mv rl tx-diff transmitter differential return loss 10 10 db 0.05 - 1.25ghz 8 db 1.25 - 2.5ghz rl tx-cm transmitter common mode return loss 66db z tx-diff-dc dc differential tx impedance 80 100 120 120 ? vtx-cm-acpp peak-peak ac common na 100 mv v tx-dc-cm transmit driver dc common mode voltage 0 3.6 0 3.6 v v tx-rcv-detect the amount of voltage change allowed during receiver detec- tion 600 600 mv i tx-short transmitter short circuit current limit 090 90ma table 20 dc electrical characteristics (part 1 of 4)
idt 89HPES32NT8BG2 datasheet 21 of 35 december 17, 2013 serial link (cont.) pcie receive v rx-diffp-p differential input voltage (peak- to-peak) 175 1200 120 1200 mv rl rx-diff receiver differential return loss 10 10 db 0.05 - 1.25ghz 8 1.25 - 2.5ghz rl rx-cm receiver common mode return loss 66db z rx-diff-dc differential input impedance (dc) 80 100 120 refer to return loss spec ? z rx--dc dc common mode impedance 40 50 60 40 60 ? z rx-comm-dc powered down input common mode impedance (dc) 200k 350k 50k ? z rx-high-imp- dc-pos dc input cm input impedance for v>0 during reset or power down 50k 50k ? z rx-high-imp- dc-neg dc input cm input impedance for v<0 during reset or power down 1.0k 1.0k ? v rx-idle-det- diffp-p electrical idle detect threshold 65 175 65 175 mv v rx-cm-acp receiver ac common-mode peak voltage 150 150 mv v rx-cm-acp pcie refclk c in input capacitance 1.5 ? 1.5 ? pf other i/os low drive output i ol ?2.5? ?2.5 ? mav ol = 0.4v i oh ?-5.5? ?-5.5 ? mav oh = 1.5v high drive output i ol ?12.0? ?12.0 ? mav ol = 0.4v i oh ? -20.0 ? ? -20.0 ? ma v oh = 1.5v schmitt trigger input (sti) v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? input v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? 3.3v output low voltage v ol ??0.4 ?0.4 vi ol = 8ma for jtag_tdo and gpio pins 3.3v output high volt- age v oh 2.4 ? ? 2.4 ? ? v i oh = 8ma for jtag_tdo and gpio pins i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 table 20 dc electrical characteristics (part 2 of 4)
idt 89HPES32NT8BG2 datasheet 22 of 35 december 17, 2013 capacitance c in ? ? 8.5 ? ? 8.5 pf ? i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 table 20 dc electrical characteristics (part 3 of 4)
idt 89HPES32NT8BG2 datasheet 23 of 35 december 17, 2013 absolute maximum voltage rating warning: for proper and reliable operation in adherence with this data s heet, the device should not exceed the recommended operating vol tages in table 16 . the absolute maximum operating voltages in table 21 are offered to provide guidelines fo r voltage excursions outside the recommended voltage ranges. device functionality is not guaranteed at these conditions and sustained op eration at these values or any expos ure to voltages outside the maximum range may adversely affect device functionality and reliability. smbus characterization leakage inputs ? ? + 10 ? ? + 10 ? av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 ? ? + 10 ? av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 ? ? + 80 ? av dd i/o (max) 1. minimum, typical, and maximum values meet the re quirements under pci express base specification 2.1. core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply 1.5v 1.5v 4.6v 1.5v 4.6v table 21 pes32nt8bg2 absolute maximum voltage rating symbol parameter smbus 2.0 char. data 1 unit 3v 3.3v 3.6v dc parameter for sda pin v il input low 1.16 1.26 1.35 v v ih input high 1.56 1.67 1.78 v v ol@350ua output low 15 15 15 mv i ol@0.4v 23 24 25 ma i pullup current source ? ? ? ? a i il_leak input low leakage 0 0 0 ? a i ih_leak input high leakage 0 0 0 ? a table 22 smbus dc characterization data (part 1 of 2) i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 table 20 dc electrical characteristics (part 4 of 4)
idt 89HPES32NT8BG2 datasheet 24 of 35 december 17, 2013 dc parameter for scl pin v il (v) input low 1.11 1.2 1.31 v v ih (v) input high 1.54 1.65 1.76 v i il_leak input low leakage 0 0 0 ? a i ih_leak input high leakage 0 0 0 ? a 1. data at room and hot temperature. symbol parameter smbus @3.3v 10% 1 1. data at room and hot temperature. unit min max f scl clock frequency 5 600 khz t buf bus free time between stop and start 3.5 ? ? s t hd:sta start condition hold time 1 ? ? s t su:sta start condition setup time 1 ? ? s t su:sto stop condition setup time 1 ? ? s t hd:dat data hold time 1 ? ns t su:dat data setup time 1 ? ns t timeout detect clock low time out ? 74.7 ms t low 2 2. t low and t high are measured at f scl = 135 khz. clock low period 3.7 ? ? s t high 2 clock high period 3.7 ? ? s t f clock/data fall time ? 72.2 ns t r clock/data rise time ? 68.3 ns t por@10khz time which a device must be operational after power-on reset 20 ? ms table 23 smbus ac timing data symbol parameter smbus 2.0 char. data 1 unit 3v 3.3v 3.6v table 22 smbus dc characterization data (part 2 of 2)
idt 89HPES32NT8BG2 datasheet 25 of 35 december 17, 2013 package pinout ? 484-bga signal pinout for the pes32nt8bg2 the following table lists the pin numbers and signal names for the pes32nt8bg2 devic e. note: pins labeled nc are no connection. pin function alt. pin function alt. pin function alt. a1 v ss b5 v ss c9 v ss a2 v dd i/o b6 pe06tn1 c10 pe06rn0 a3 pe06tp3 b7 pe06tn0 c11 v ss a4 pe06tp2 b8 v ss c12 v ss a5 v ss b9 gclkn0 c13 pe04rn3 a6 pe06tp1 b10 v ss c14 v ss a7 pe06tp0 b11 pe04tn3 c15 pe04rn2 a8 v ss b12 pe04tn2 c16 refres02 a9 gclkp0 b13 v ss c17 v ss a10 v ss b14 p04clkn c18 pe04rn0 a11 pe04tp3 b15 v ss c19 perstn a12 pe04tp2 b16 pe04tn1 c20 jtag_trst_n a13 v ss b17 pe04tn0 c21 ssmbdat a14 p04clkp b18 v dd i/o c22 v dd i/o a15 v ss b19 msmbclk d1 v ss a16 pe04tp1 b20 jtag_tms d2 v ss a17 pe04tp0 b21 ssmbclk d3 v ss a18 v dd i/o b22 jtag_tck d4 v ss a19 msmbdat c1 v ss d5 pe06rp3 a20 jtag_tdo c2 v dd i/o d6 pe06rn2 a21 clkmode1 c3 v ss d7 v ss a22 ssmbaddr2 c4 v ss d8 pe06rp1 b1 v ss c5 pe06rn3 d9 v ss b2 v dd i/o c6 v ss d10 pe06rp0 b3 pe06tn3 c7 v ss d11 refrespll b4 pe06tn2 c8 pe06rn1 d12 v ss table 24 pes32nt8bg2 signal pin-out (part 1 of 7)
idt 89HPES32NT8BG2 datasheet 26 of 35 december 17, 2013 d13 pe04rp3 e17 pe04rp1 f21 pe02tn2 d14 v ss e18 v dd peha f22 pe02tp2 d15 pe04rp2 e19 v ss g1 pe08tp0 d16 v ss e20 v ss g2 pe08tn0 d17 pe04rn1 e21 pe02tn3 g3 v ss d18 pe04rp0 e22 pe02tp3 g4 pe08rn1 d19 v ss f1 v ss g5 pe08rp1 d20 jtag_tdi f2 v ss g6 v dd pea d21 v dd i/o f3 pe08rn0 g7 v ss d22 v dd i/o f4 pe08rp0 g8 v dd core e1 v ss f5 v dd peha g9 v dd core e2 v ss f6 v dd peha g10 v ss e3 v ss f7 v dd peha g11 v dd core e4 v ss f8 v dd pea g12 v dd core e5 v dd peha f9 v dd peta g13 v ss e6 pe06rp2 f10 v dd pea g14 v dd core e7 v dd pea f11 v dd pea g15 v dd core e8 v dd pea f12 v dd peta g16 v ss e9 v dd peta f13 v dd peta g17 v dd pea e10 v dd pea f14 v dd pea g18 v dd pea e11 refres03 f15 v dd pea g19 pe02rp3 e12 v dd peta f16 v dd pea g20 pe02rn3 e13 nc f17 v dd peha g21 v ss e14 v ss f18 v dd peha g22 v ss e15 v dd pea f19 v dd peha h1 pe08tp1 e16 v ss f20 v ss h2 pe08tn1 pin function alt. pin function alt. pin function alt. table 24 pes32nt8bg2 signal pin-out (part 2 of 7)
idt 89HPES32NT8BG2 datasheet 27 of 35 december 17, 2013 h3 refres05 j7 v ss k11 v dd core h4 v ss j8 v dd core k12 v dd core h5 v dd pea j9 v dd core k13 v ss h6 v dd pea j10 v ss k14 v dd core h7 v ss j11 v dd core k15 v dd core h8 v dd core j12 v dd core k16 v ss h9 v dd core j13 v ss k17 v dd peta h10 v ss j14 v dd core k18 refres01 h11 v dd core j15 v dd core k19 pe02rp1 h12 v dd core j16 v ss k20 pe02rn1 h13 v ss j17 v dd peta k21 v ss h14 v dd core j18 v dd peta k22 v ss h15 v dd core j19 refres00 l1 pe08tp3 h16 v ss j20 nc l2 pe08tn3 h17 v dd pea j21 p02clkn l3 v ss h18 pe02rp2 j22 p02clkp l4 v ss h19 pe02rn2 k1 pe08tp2 l5 v dd pea h20 v ss k2 pe08tn2 l6 v dd pea h21 p00clkn k3 v ss l7 v ss h22 p00clkp k4 pe08rn3 l8 v dd core j1 v ss k5 pe08rp3 l9 v dd core j2 v ss k6 v dd peta l10 v ss j3 pe08rn2 k7 v ss l11 v dd core j4 pe08rp2 k8 v dd core l12 v dd core j5 v dd peta k9 v dd core l13 v ss j6 v dd peta k10 v ss l14 v dd core pin function alt. pin function alt. pin function alt. table 24 pes32nt8bg2 signal pin-out (part 3 of 7)
idt 89HPES32NT8BG2 datasheet 28 of 35 december 17, 2013 l15 v dd core m19 v ss p1 pe12tp1 l16 v ss m20 v ss p2 pe12tn1 l17 v dd pea m21 pe02tn0 p3 v ss l18 pe02rp0 m22 pe02tp0 p4 v ss l19 pe02rn0 n1 pe12tp0 p5 v dd peta l20 v ss n2 pe12tn0 p6 v dd peta l21 pe02tn1 n3 refres04 p7 v ss l22 pe02tp1 n4 pe12rn1 p8 v dd core m1 v ss n5 pe12rp1 p9 v dd core m2 v ss n6 v dd pea p10 v ss m3 pe12rn0 n7 v ss p11 v dd core m4 pe12rp0 n8 v dd core p12 v dd core m5 v dd pea n9 v dd core p13 v ss m6 v dd pea n10 v ss p14 v dd core m7 v ss n11 v dd core p15 v dd core m8 v dd core n12 v dd core p16 v ss m9 v dd core n13 v ss p17 v dd pea m10 v ss n14 v dd core p18 pe00rp2 m11 v dd core n15 v dd core p19 pe00rn2 m12 v dd core n16 v ss p20 v ss m13 v ss n17 v dd pea p21 pe00tn3 m14 v dd core n18 v dd pea p22 pe00tp3 m15 v dd core n19 pe00rp3 r1 v ss m16 v ss n20 pe00rn3 r2 v ss m17 v dd pea n21 v ss r3 pe12rn2 m18 v dd pea n22 v ss r4 pe12rp2 pin function alt. pin function alt. pin function alt. table 24 pes32nt8bg2 signal pin-out (part 4 of 7)
idt 89HPES32NT8BG2 datasheet 29 of 35 december 17, 2013 r5 v dd peta t9 v dd core u13 v dd pea r6 v dd peta t10 v ss u14 v dd pea r7 v ss t11 v dd core u15 v dd peta r8 v dd core t12 v dd core u16 v dd pea r9 v dd core t13 v ss u17 v dd peha r10 v ss t14 v dd core u18 pe00rp0 r11 v dd core t15 v dd core u19 pe00rn0 r12 v dd core t16 v ss u20 v ss r13 v ss t17 v dd peta u21 pe00tn1 r14 v dd core t18 v dd peta u22 pe00tp1 r15 v dd core t19 pe00rp1 v1 v dd i/o r16 v ss t20 pe00rn1 v2 v dd i/o r17 v dd peta t21 v ss v3 pe12rn3 r18 v dd peta t22 v ss v4 pe12rp3 r19 v ss u1 pe12tp3 v5 v ss r20 v ss u2 pe12tn3 v6 pe16rp1 r21 pe00tn2 u3 v ss v7 v ss r22 pe00tp2 u4 v ss v8 v dd pea t1 pe12tp2 u5 v dd peha v9 v dd pea t2 pe12tn2 u6 v dd peha v10 v ss t3 v ss u7 v dd pea v11 v dd peta t4 v ss u8 v dd pea v12 v ss t5 v dd peha u9 v dd pea v13 v dd pea t6 v dd peha u10 v dd peta v14 pe20rp1 t7 v ss u11 v dd peta v15 v dd peta t8 v dd core u12 v dd pea v16 v dd pea pin function alt. pin function alt. pin function alt. table 24 pes32nt8bg2 signal pin-out (part 5 of 7)
idt 89HPES32NT8BG2 datasheet 30 of 35 december 17, 2013 v17 v dd peha w21 v dd i/o aa3 swmode0 v18 v dd peha w22 v dd i/o aa4 v ss v19 v ss y1 stk0cfg0 aa5 v dd i/o v20 v ss y2 stk3cfg0 aa6 pe16tn0 v21 pe00tn0 y3 v ss aa7 pe16tn1 v22 pe00tp0 y4 v dd i/o aa8 v ss w1 v ss y5 pe16rn0 aa9 pe16tn2 w2 stk1cfg0 y6 v ss aa10 pe16tn3 w3 stk2cfg0 y7 v ss aa11 v ss w4 v dd i/o y8 pe16rn2 aa12 gclkn1 w5 pe16rp0 y9 v ss aa13 v ss w6 pe16rn1 y10 v ss aa14 pe20tn0 w7 refres06 y11 pe16rn3 aa15 pe20tn1 w8 pe16rp2 y12 v ss aa16 v ss w9 v ss y13 pe20rn0 aa17 pe20tn2 w10 v ss y14 v ss aa18 pe20tn3 w11 pe16rp3 y15 refres07 aa19 v ss w12 v ss y16 pe20rn2 aa20 gpio_03 2 w13 pe20rp0 y17 v ss aa21 gpio_04 2 w14 pe20rn1 y18 v ss aa22 gpio_05 2 w15 v ss y19 pe20rn3 ab1 swmode1 w16 pe20rp2 y20 gpio_06 2 ab2 rsthalt w17 v ss y21 gpio_07 2 ab3 swmode2 w18 v dd peha y22 gpio_08 2 ab4 swmode3 w19 pe20rp3 aa1 clkmode0 ab5 v dd i/o w20 v dd i/o aa2 gclkfsel ab6 pe16tp0 pin function alt. pin function alt. pin function alt. table 24 pes32nt8bg2 signal pin-out (part 6 of 7)
idt 89HPES32NT8BG2 datasheet 31 of 35 december 17, 2013 ab7 pe16tp1 ab13 v ss ab19 v ss ab8 v ss ab14 pe20tp0 ab20 gpio_00 2 ab9 pe16tp2 ab15 pe20tp1 ab21 gpio_01 2 ab10 pe16tp3 ab16 v ss ab22 gpio_02 2 ab11 v ss ab17 pe20tp2 ab12 gclkp1 ab18 pe20tp3 pin function alt. pin function alt. pin function alt. table 24 pes32nt8bg2 signal pin-out (part 7 of 7)
idt 89HPES32NT8BG2 datasheet 32 of 35 december 17, 2013 pes32nt8bg2 package drawing ? 484-pin hl/hlg484
idt 89HPES32NT8BG2 datasheet 33 of 35 december 17, 2013 pes32nt8bg2 package drawing ? page two note: nominal package height: 2.63mm minimum package height: 2.53mm.
idt 89HPES32NT8BG2 datasheet 34 of 35 december 17, 2013 revision history october 27, 2010 : initial publication of final data sheet. november 11, 2010 : added zb silicon on ordering page. january 26, 2011 : in table 18 , power consumption, revised io ( and total) power numbers in full sw ing section and added half swing section. adjusted p value in table 19 . march 9, 2011 : in table 10 , deleted ?external pull-down? from the notes column for jtag_trst_n. march 28, 2011 : in tables 16 and 17, added v dd peta to footnote #1. may 20, 2011 : removed za silicon and added zc to order page and codes. november 7, 2011 : revised values in table 18 , power consumption, and updated power dissipation value in table 19 . november 29, 2011 : added new tables 22 and 23, smbus characterization and timing. march 14, 2012 : in table 3 , revised description for gclkn/p signals. april 16, 2013 : in table 20 , added 3.3v output voltage parameters under other i/os category. may 16, 2013 : added note after table 11. in table 20 , added information in the conditions column for the 3.3v parameters. december 17, 2013 : added footnote 2 to table 23 .
corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 www.idt.com for tech support: email: ssdhelp@eng.idt.com ? 35 of 35 december 17, 2013 idt 89HPES32NT8BG2 datasheet disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, wh ether express or implied, including, but not limited to, the suit ability of idt?s products for any particular purpose, an impli ed warranty of merchantability, or non-infringe ment of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. ordering information valid combinations 89h32nt8bg2zbhl 484-ball fcbga package, commercial temp. 89h32nt8bg2zchl 484-ball fcbga package, commercial temp. 89h32nt8bg2zbhlg 484-ball green fc bga package, commercial temp. 89h32nt8bg2zchlg 4 84-ball green fcbga package, commercial temp. 89h32nt8bg2zbhli 484-ball fcbga package, industrial temp. 89h32nt8bg2zchli 484-ball fcbga package, industrial temp. 89h32nt8bg2zbhlgi 484-ball green fcbga package, industrial temp. 89h32nt8bg2zchlgi 484-ball green fcbga package, industrial temp. nn a nnaana aaa a operating voltage product package temp range h product family 89 serial switching product 32nt8b 32-lane, 8-port 1.0v core voltage detail legend a = alpha character n = numeric character aa device revision an generation series g2 pcie gen 2 484-ball fcbga hl 484-ball fcbga, green hlg blank commercial temperature (0c to +70c ambient) i industrial temperature (-40 c to +85 c ambient) zb zb revision zc zc revision

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